Dedicated Clock Pin Out

That's right, each device has one dedicated pin that can be associated with each pll. This pin is hardwired within the fpga and cannot be assigned to any other pin. However the output of the pll can be routed to any io pin through a clock net it's just that the delay will be longer.

The pins are defined in the pin file for each device as pll#_out in the optional functions column.

The device handbook is another place that documents which dedicated PLL device pins go with each PLL.

It might be OK for your design to use a nondedicated PLL output pin. Besides the delay from the PLL to the pin, the jitter is affected. I expect you got a warning like this:

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Warning: PLL "my_pll:pll|altpll:altpll_component|pll" output port clk[1] feeds output pin "pll_output" via non-dedicated routing -- jitter performance depends on switching rate of other design elements. Use PLL dedicated clock outputs to ensure jitter performance

--- Quote End ---

If your DAC can tolerate more jitter than is in the FPGA device handbook spec for the PLL output, then you might be OK with the present pin-out.

The help for that warning:

--- Quote Start ---

PLL "<name>" output port <name> feeds output pin "<name>" via non-dedicated routing -- jitter performance depends on switching rate of other design elements. Use PLL dedicated clock outputs to ensure jitter performance

--------------------------------------------------------------------------------

CAUSE: The specified clock port of the specified PLL feeds an output pin via non-dedicated routing. This may cause jitter performance to degrade due to noise from multiple switching design elements. Use PLL dedicated clock outputs to ensure jitter performance.

ACTION: To avoid receiving this message, modify the design so that the specified clock ports of the specified PLL do not feed an output pin or use the PLL dedicated clock outputs to feed an output pin for better jitter performance.

--- Quote End ---

Hi,

I am having the same issue with a cyclone III device. I want to take the C0 output from a PLL and drive it through a buffer (altclkctra) to an I/O pin. The cyclone III has 4 PLL´s but how do I know which PLL is being used. I initially thought the PLL closest to the the dedicated clock input feeding the PLL input, but after assigning the output to the dedicated output of the 4 PLL´s, I cannot find the match and I still recieve the following error:

Warning: PLL "Main_PLL:Main_PLL_Inst|altpll:altpll_component|Main_PLL_altpll:auto_generated|pll1" output port clk[0] feeds output pin "WF_DCLK~output" via non-dedicated routing -- jitter performance depends on switching rate of other design elements. Use PLL dedicated clock outputs to ensure jitter performance

The output is assigned the output of the PLL directly, so i dont understand what it means by "via non-dedictaed routing".

Is there anyway of knowing which PLL is actually being used?

Thanks for any advice

Hello Ardni,

I am not sure I can be much help with this anymore. I haven't worked with the Cyclone (or Quartus) for nearly a year now. I remember though, getting that exact warning you are getting.

The only solution I remember (and I don't even have Quartus installed to check) was something in the settings of the whole system. You need to somehow specify these channels in the settings to use dedicated routing to ensure proper timing.

Hopefully that points you in the direction of a solution. Sorry again, that I am not much help.

Good luck!

Dave

Hi Ardni,

I am fairly new to this and have only used stratix parts, but can you use floorplanner to locate which pll is being used, and then make sure that that pll has dedicated routing to the output pin?

You can easily find the output pin in the floorplanner by opening the pin planner, right clicking on your output pin, and selecting locate in floorplanner. You should then be able to trace it back to the pll to see which one Quartus is using.

Hope that helps

Thank you dtietz and PrefectD for the responses.

I had a look in the floorplanner and it seems as though Quartus is using PLL1, as I expected. However when I assign the clk pin to the output pin of this PLL I continue to get the warning.

I´m sure its something simple, I´m out of the office for a few days so I won´t be able to work with it, but early next week I´ll have a proper read of the documnetation to see if anything is specified there. I´ll post whatever solution I find but in the meantime if anyone has been able to resolve this issue previously please let me know.

Thanks again.