Dedicated Clock Pin Out

Hi,

I am having the same issue with a cyclone III device. I want to take the C0 output from a PLL and drive it through a buffer (altclkctra) to an I/O pin. The cyclone III has 4 PLL´s but how do I know which PLL is being used. I initially thought the PLL closest to the the dedicated clock input feeding the PLL input, but after assigning the output to the dedicated output of the 4 PLL´s, I cannot find the match and I still recieve the following error:

Warning: PLL "Main_PLL:Main_PLL_Inst|altpll:altpll_component|Main_PLL_altpll:auto_generated|pll1" output port clk[0] feeds output pin "WF_DCLK~output" via non-dedicated routing -- jitter performance depends on switching rate of other design elements. Use PLL dedicated clock outputs to ensure jitter performance

The output is assigned the output of the PLL directly, so i dont understand what it means by "via non-dedictaed routing".

Is there anyway of knowing which PLL is actually being used?

Thanks for any advice