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Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
10 years ago

declaring objects in verilog

sorry wrong post

1 Reply

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    10 years ago

    You are looking for signals in a submodule bfm_common that is never called or defined.

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