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Altera_Forum
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13 years ago

Declaration ?

library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; use ieee.std_logic_unsigned.ALL; entity uppgift_3b is port ( clk : in std_logic; -- CLOCK_50 ...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
13 years ago

You have declared two different types for the same name. (rom_type is declared twice)

Change the first to:

TYPE ram_type IS ARRAY (0 TO 63) OF std_logic_vector(2 DOWNTO 0);

and then declare your ram as:

SIGNAL RAM_mem: ram_type;

Hope this helps