Declaration ?

library ieee;

use ieee.std_logic_1164.all;

use ieee.numeric_std.all;

use ieee.std_logic_unsigned.ALL;

entity uppgift_3b is

port

(

clk : in std_logic; -- CLOCK_50

-- RAM

addr_ram : in std_logic_vector(2 downto 0); -- addr in slide switches

data_ram : in std_logic_vector(1 downto 0); -- data in slide switches

we_ram : in std_logic; -- from slide switches

q_ram : out std_logic_vector(1 downto 0); -- data out to leds

---ROM

addr_rom : in std_logic_vector(1 downto 0); -- addr in slide switches

q_rom : out std_logic_vector(1 downto 0) -- data out to leds

);

end entity;

architecture BLOCK_RAM_ROM_FPGA OF uppgift_3b IS

---- RAM

TYPE rom_type IS ARRAY (0 TO 63)OF

std_logic_vector (2 downto 0);

SIGNAL RAM_mem: mem_type; ----- < (*) i must declare this i dont know how ? -----

--- ROM

TYPE rom_type IS ARRAY (0 TO 3**2 - 1) OF STD_LOGIC_VECTOR (2 DOWNTO 0);

CONSTANT ROM_mem: rom_type := (

"111", -- adr 0

"000",

"101",

"100",

"010",

"110",

"100", -- adr 6

OTHERS => "000");

BEGIN

RAM: PROCESS (clk)

BEGIN

IF rising_edge(clk) THEN

IF (we_ram = '1') THEN

RAM_mem(conv_integer(addr_ram)) <= data_ram;

END IF;

q_ram <= RAM_mem(conv_integer(addr_ram));

END IF;

END PROCESS;

----------------------------------- ROM ----------------------

ROM: PROCESS (clk)

BEGIN

IF rising_edge (clk) THEN

q_rom <= rom_mem(conv_integer(addr_rom));

END IF;

END PROCESS;

END ARCHITECTURE Block_RAM_ROM_FPGA;

(*)Error (10482): VHDL error at uppgift_3b.vhd(25): object "mem_type" is used but not declared