Altera_ForumHonored Contributor10 years agoDe2 Verilog HDL LCD coding problem Good day. we are currently doing a project using altera de2 that requires us to use the lcd. we have 3 .v files and VErilog3 is our top module. module Verilog3( //////// CLOCK //////...Show More
Altera_ForumHonored Contributor10 years agoI think you should use SignalTap II tool for debugging your problem. Long.
Recent DiscussionsConnection bit order between hierarchyHow to fix Error(23782): Failed to find an expected reportSolvedQuartus 22.1 and 23.1 Synthesis ErrorCould not link 'vsim_auto_compile.dll' error troubleshooting.Failed to run ip-setup-simulation: