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Honored Contributor
13 years agoAn HDL file is *not* sufficient. You also need to tell Quartus what pins LEDR and SW are on the FPGA, otherwise Quartus assigns a couple of random pins.
Use the Pin Planner to view the pins used on the FPGA. I posted a DE2 example design in this thread: http://www.alteraforum.com/forum/showthread.php?t=33462 Take a look at it. Look at the pin constraints file, and look at your schematic. I believe there are a couple of revision of the DE2 board, so check the schematic for your design against the list of pins and see if they match. If they do, then run the synthesis script and download it. You can then use that design as template (its in VHDL), or you can convert it to Verilog. Cheers, Dave