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How I can " Quartus to configure the EPCS device on the board"?
Are there any requirements to download the verilog hdl file on the EPCS16?
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Your question indicates that you have not spent enough timing studying how FPGAs work. Please go and read some more.
FPGA synthesis tools read HDL files and produce configuration files. The configuration file with the extension .sof is what you download directly to the FPGA via JTAG.
The .sof file can be converted to a format that is compatible with the EPCS EEPROMs, but the required format depends on whether your board has an active serial header, or uses the JTAG header and JTAG indirect mode, which first loads the FPGA, and then uses JTAG to program the EPCS EEPROM.
These comments should contain enough key-words for you to go back to the DE2 and Quartus documentation and find the details you need.
Cheers,
Dave