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Altera_Forum's avatar
Altera_Forum
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15 years ago

DE2-70 SOPC SDRAM compile error

Hi.

I study with DE2-70 & "using the sdram memory on altera's de2-70 board

with verilog design" manual.

I practiced sopc & sdram example but i had some error messages as shown in the attached image.

I assigned the pin map by importing "de2-70 pin assignments.csv" file,

and coded verilog source file using pin node name.

please let me how can i solve this problem..

Thanks in advance.

https://www.alteraforum.com/forum/attachment.php?attachmentid=2873

https://www.alteraforum.com/forum/attachment.php?attachmentid=2874

2 Replies

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    15 years ago

    I do not programm in Verilog, but from my understanding the datapins should be bidirectional?! (you can read it in the sopc description: "dq to and from the...") I think the instanciation for that in verilog is "inout [15:0] dram_dq;" perhaps give it a try, but I am not sure.

    Have a nice day, Peter.
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    15 years ago

    --- Quote Start ---

    I do not programm in Verilog, but from my understanding the datapins should be bidirectional?! (you can read it in the sopc description: "dq to and from the...") I think the instanciation for that in verilog is "inout [15:0] dram_dq;" perhaps give it a try, but I am not sure.

    Have a nice day, Peter.

    --- Quote End ---

    I didn't find my mistake about "inout" & "input"..

    Thanks for your apply!