DE2-115 Lab 1 Help

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hi guys I just purchased the DE2-115 board and embarrassingly I have run into an error into the first lab itself:

We are supposed to implement a multiplexor so that the green LEDs mimic the input of either switches 0 - 7 or 8 - 15 based on the select input on switch 17. Heres my code; please tell me why only the x input is being passed perfectly to the green LEDs but when s is high only SW[8] is passed to the green LEDS from y inputs. Thanks!!!

:

Module TrialTwo (SW, LEDG, LEDR);

Input [17:0] SW;

Output [17:0] LEDR;

Output [7:0] LEDG;

Wire [7:0] x;

Wire [7:0] y;

Wire [7:0] m;

Wire s;

Assign x[7:0] = SW[7:0];

Assign x[7:0] = SW[15:8];

Assign s = SW[17];

Assign m = (~s&x) | (s&y);

Assign LEDG = m;

Assign LEDR = SW;

endmodule

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you are not driving y but x is driven twice?

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you are not driving y but x is driven twice?

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eerrr right thanks lol

I have changed it so that x and y are both being driven yet the problem persists. Additionally I tried to do the 4th part of the same lab and no matter what inputs I give the 7-seg display shows all segments high. This problem persisted even after i changed the code so that the display should show six whatever the input. Is it possible I need to delete the old .sof file before recompiling or something? Heres my code, please help!:

module TrialTwoPointTwo (SW, LEDR, HEX0);

input [17:0] SW;

output [17:0] LEDR;

output [0:6] HEX0;

wire [2:0] m;

assign LEDR = SW;

mux3bit5to1 M0(SW[17:15], SW[14:12], SW[11:9], SW[8:6], SW[5:3], SW[2:0], m);

char7seg H0(m, HEX0_D);

endmodule

module mux3bit5to1(A, B, C, D, E, F, O);

input [2:0] A, B, C, D, E, F;

//input [3:0] KEY;

output [2:0] O;

wire [2:0] a1;

wire [2:0] b1;

wire [2:0] c1;

wire [2:0] d1;

wire [2:0] e1;

wire [2:0] f1;

wire [2:0] o1;

assign a1 = A;

assign b1 = B;

assign c1 = C;

assign d1 = D;

assign e1 = E;

assign f1 = F;

assign o1 = (~a1[0] & ~a1[1] & ~a1[2] & b1) | (~a1[0] & ~a1[1] & a1[2] & c1) | (~a1[0] & a1[1] & ~a1[2] & d1) | (~a1[0] & a1[1] & a1[2] & e1) | (~a1[0] & a1[1] & a1[2] & f1);

assign O = o1;

endmodule

module char7seg(c, Display);

input [2:0] c;

output [0:6] Display;

wire [0:6] Ini;

assign Ini[0] = 1'b1;//(~c[0] & ~c[1] & c[2])|(~c[0] & c[1] & c[2]);

assign Ini[1] = 1'b0;//(~c[0] & ~c[1] & ~c[2])|(~c[0] & c[1] & c[2]);

assign Ini[2] = 1'b1;//(~c[0] & ~c[1] & ~c[2])|(~c[0] & c[1] & c[2]);

assign Ini[3] = 1'b1;//(~c[0] & ~c[1] & c[2])|(~c[0] & c[1] & c[2]) | (~c[0] & c[1] & ~c[2]);

assign Ini[4] = 1'b1;//(~c[0] & ~c[1] & c[2])|(~c[0] & c[1] & c[2]) | (~c[0] & c[1] & ~c[2])|(~c[0] & ~c[1] & ~c[2]);

assign Ini[5] = 1'b1;//(~c[0] & ~c[1] & c[2])|(~c[0] & c[1] & c[2]) | (~c[0] & c[1] & ~c[2])|(~c[0] & ~c[1] & ~c[2]);

assign Ini[6] = 1'b1;//(~c[0] & ~c[1] & ~c[2])|(~c[0] & ~c[1] & c[2]);

assign Display[0:6] = Ini[0:6];

endmodule