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Altera_Forum
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10 years ago

De0 sdram vhdl

Hi everybody, I tried to write a VHDL code for the SDRAM controller based of the Hamster one in: http://hamsterworks.co.nz/mediawiki/index.php/simple_sdram_controller The next thing I would ...
Altera_Forum's avatar
Altera_Forum
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10 years ago

Thank you Linas for your reply. I understood the data-sheet of my chip and also write the code. The problem that I have is how to generate pattern to test my memory.

I used a timer to generate an interruption, when it's activated I write a DATA in a specified address. And when the interruption is deactivated I read the data that was written. Unfortunately, it doesn't work for me.

Note: i did not use nios neither jtag, only VHDL coding.

Best regards