DDR3 variation file generation on Q10.1

Hi

BACKGROUND:

I'm trying to compile a project to run on the Arria II GX development kit.

the project includes an SOPC system with Nios DMAs and RAM. since the SRAM is too small I need to use the DDR3 memory.

I've copied the DDR3 configuration from the example project and run my design (made sure to pass timing).

everything looked ok except from the DMAs operation. I strongly believe this has something to do with the fact the the DDR3 local bus is 64 bit while my Nios and periphery are 32 bit.

PROBLEM

when I try to change the parameter of the DQ bus width from the SOPC, it seems that only the SOPC changes, but the RAM.v variations file still shows 16 bit DQ bus. this causes mismatch errors in synthesis.

when I try to change it through the Mega Wizard editor, it changes a wrapper file, but not the variation file...

any ideas?