Altera_Forum
Honored Contributor
Honored ContributorDDR2 altmemphy timing warning
Hi,
I'm using an DDR2 altmemphy instantiation and get the following warnings (please see below) when I compile: Can/should these be ignored? I am having some flakiness with the DDR2 which varies from one compile to the next i.e. when I alter unrelated logic and re-compile I sometimes get good results and sometimes not so good. My guess is that there is something which is not fully constrained, but apart from the sdc provided by the altmemphy instantiation I think I'm deriving all clocks i.e. I use derive_pll_clocks in my sdc. I've lived with these warnings for quite a while and as far as I can tell, the flakiness has only started since my project has gone past a certain point/complexity in development. P.S. is the order of the sdc files important? P.P.S. Is the jtag clock warning something (which everyone I know seems to ignore), something which actually should be ignored? Many thanks, D Warning: The master clock for this clock assignment could not be derived. Clock: altera_internal_jtag|tckutap was not created. Warning: No clocks found on or feeding the specified source node: altera_internal_jtag|tck Warning: Node: DSP_Delay_RAM_32bit_q9_phy:path_delay|AMP_9_175_32bit_1Gbit:inst|AMP_9_175_32bit_1Gbit_alt_mem_phy:AMP_9_175_32bit_1Gbit_alt_mem_phy_inst|AMP_9_175_32bit_1Gbit_alt_mem_phy_clk_reset:clk|scan_clk was determined to be a clock but was found without an associated clock assignment. Warning: Node: altera_reserved_tck was determined to be a clock but was found without an associated clock assignment. Warning: Node: DSP_Delay_RAM_32bit_q9_phy:input_output_delay|AMP_9_175_32bit_1Gbit:inst|AMP_9_175_32bit_1Gbit_alt_mem_phy:AMP_9_175_32bit_1Gbit_alt_mem_phy_inst|AMP_9_175_32bit_1Gbit_alt_mem_phy_clk_reset:clk|scan_clk was determined to be a clock but was found without an associated clock assignment. Warning: Node: DELAY_1_DQS[0] was determined to be a clock but was found without an associated clock assignment. Warning: Node: DELAY_0_DQS[0] was determined to be a clock but was found without an associated clock assignment. Warning: Node: DELAY_1_DQS[1] was determined to be a clock but was found without an associated clock assignment. Warning: Node: DELAY_1_DQS[2] was determined to be a clock but was found without an associated clock assignment. Warning: Node: DELAY_1_DQS[3] was determined to be a clock but was found without an associated clock assignment. Warning: Node: DELAY_0_DQS[1] was determined to be a clock but was found without an associated clock assignment. Warning: Node: DELAY_0_DQS[2] was determined to be a clock but was found without an associated clock assignment. Warning: Node: DELAY_0_DQS[3] was determined to be a clock but was found without an associated clock assignment.
