DDR Fitter error

Hi guys,

I'm getting the following compilation report on a new project: "Critical Warning: Fitter could not properly route signals from DQ I/Os to DQ capture registers because the DQ capture registers are not placed next to their corresponding DQ I/Os

Info: DQ capture register ddrbot:DDRBOT_inst|ddrbot_controller_phy:ddrbot_controller_phy_inst|ddrbot_phy:alt_mem_phy_inst|ddrbot_phy_alt_mem_phy:ddrbot_phy_alt_mem_phy_inst|ddrbot_phy_alt_mem_phy_clk_reset:clk|altddio_bidir:DDR_CLK_OUT[0].ddr_clk_out_p|ddio_bidir_cmg:auto_generated|input_cell_h[0] at (65, 1) is not assigned to the adjacent LAB of the corresponding DQ I/O DDRBOTCLK[0]~input at (73, 0)

The design is a EP3C55F780, with a 32bit DDR1 in the top and bottom banks. What I've found with investigation:

- It's only related to the bottom bank, the top bank is fine despite being very similarly implemented.

- The DDR Clock is connected to the bank PLL_OUT pins. When I move them to any other diff pair, the problem disappears but then it fails the timing requirements.

- There are six possible byte sets (8xDQ+DM+DS) of which I use four, when I changed two of it the problem was still there.

Any ideas would be much appreciated.

Pierre