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Honored Contributor
Honored ContributorDCFIFO readings incorrect using different reading clock
Hi, I am attempting to use DCFIFO megafunction in my design, but two problems met: 1. the rdempty signal always keep high, and rdusew signals don't function, too. so I can't read data fro...
Altera_ForumHonored Contributor
Honored ContributorHi,
Debug individual blocks so you can find the mistake. Understand the timing diagram from the https://www.altera.com/en_us/pdfs/literature/ug/archives/ug-fifo-15.1.pdf and try to compare with your code. Can you attach .v file. Anand Raj Shankar (This message was posted on behalf of Intel Corporation)
