Contributordcfifo #( .intended_device_family ("Agilex"), .lpm_numwords (32), .lpm_showahead ("ON"), .lpm_type ( "dcfifo"), .lpm_width ($bits(t_cmd_data)), .lpm_widthu (6), .add_usedw_msb_bit ("ON"), .read_aclr_synch ("ON"), .write_aclr_synch ("ON"), .rdsync_delaypipe (4), .wrsync_delaypipe (4) ) cmd_dcfifo_i (
full is set 2clocks after a write
full when 29 words are in, whereas the depth is 32
Frequent ContributorHi,
Are you using FIFO parameter editor or manually instantiating the FIFO IP?
Please ensure that the input and output ports used, and the parameter values assigned are valid for the FIFO Intel® FPGA IP core you instantiate for your target device.
If still not resolved, share the Quartus project QAR with the detailed steps to replicate the issue at my end.
Thank you,
Kshitij Goel
ContributorContributor
Super ContributorThis is the info for the fifo IP including using the dual clock option. Isn't that what you asked for? https://www.intel.com/content/www/us/en/docs/programmable/683130/24-1/fifo-settings.html
Frequent ContributorFrequent ContributorHi,
As we do not receive any response from you on the previous answer that we have provided. Please login to ‘https://supporttickets.intel.com’, view details of the desire request, and post a response within the next 15 days to allow me to continue to support you. After 15 days, this thread will be transitioned to community support. The community users will be able to help you on your follow-up questions.
Thank you,
Kshitij Goel
