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Altera_Forum's avatar
Altera_Forum
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13 years ago

daft question about Verilog parameter

Hi All, Is it legal to define a new parameter based on a previously declared one ? Thanks, Mark parameter HS64x8_XINC = 86; parameter HS64x8_X0POSN = 70; parameter HS64x8_X1P...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
13 years ago

Yes you can do that.

I often do stuff like:

module module_name# (

parameter BUS_WIDTH = 32,

parameter BUS_WIDTH_DEC = clogb2(BUS_WIDTH)

)(

ports....

where clogb2 is a function so I can overload the parameter at the instantiation and have it propogate to the other parameter