Cyclone V Transceiver .QIP and .SIP - Do I Really Need Them

The QIP file is pointing to multiple Verilog/SystemVerilog files that have been created in my design from the Megawizard but this couldn't be required by the synthesis as the Cyclone V transceiver is hard IP on the silicon, I think this is my confusion - what are these generated files for?

You are probably right and just trying it and see if I get any errors during the compilation. I wanted to clean up multiple transceiver components generated i.e. transceiver, reset controller and reconfiguration controller in to a single custom VHDL file so that it is all wrapped up nicely.