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Altera_Forum's avatar
Altera_Forum
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12 years ago

Cyclone V DDR3 Controller with Uniphy

Hello,

I am new with qsys and memory configurations and was wondering if someone could please point me in the right direction. When I generate the DDR3 controller in qsys I get an input called "oct_rzqin" that I do not know what to do with. The DDR3 that I am using (MT41J256M8) has a ZQ pin that is routed to a 240 ohm resistor and then to ground as the spec sheet calls for. It seems like the FPGA oct_rzqin pin is trying to serve the same purpose but I cannot find anywhere if this is necessary or how to properly use it. The design will not compile if this pin stays unconnected.

Thanks.

1 Reply

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    12 years ago

    Hi,

    The "oct_rzqin" is not a wire to be bounded to the DDR3, but rather to a rzqin pin of your board.

    (look for it in the pinout list of your board)

    (Cyclone V GX Dev Kit : PIN_AK13)

    regards,