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Altera_Forum
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13 years ago

Cyclone IV GX: Output Skew at DDR LVDS Output

Hello, my task is to implement a source synchronous interface between a Cyclone IV GX EP4CGX50CF23C6 and an Arria V (B3 ES). Therefore I've read a lot about constraining this (AN433, Altera Web...
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Altera_Forum
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13 years ago

Unfortunately I know of no way to get a more realistic value for the output skew, and certainly nothing that Altera would stand behind. If I were to take an educated guess, I would estimate that if you keep all the data outputs clocked by the same output clock in the same sub-bank, then you could probably count on around +/- 100 ps.