Cyclone IV GX: Output Skew at DDR LVDS Output

I checked your constraints, and you did both the Rx side and the Tx side properly. Unfortunately, once Altera went to min/max timing analysis (beginning with Cyclone III/Stratix III families), source synchronous output timing has really suffered. It really is just a problem with the micro timing models that are too overly conservative. Since external memory interfaces use the same DDIO components and can run at much higher speeds (and are timed with macro model instead of micro model timing), we know this is a model problem. The best you can do is to keep your output data in the same sub-bank and use the same clock for data and clock (as you've done). It is not unusual to see output data skew at +/- 350 ps because of this problem.