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Altera_Forum
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13 years ago

Cyclone IV: Error when mixing VCCIO, VCC_CLKIN in same bank

I am trying to compile a design for the Cyclone IV GX development board, which is based on an EP4CGX1150DF31C7. This board has bank 8 wired to a VCCIO of 1.8V. But within bank 8, there's the clocking bank, 8B, with a 125MHz 2.5V LVDS clock. This bank has VCC_CLKIN wired to 2.5V (based on my reading of the schematic). According to solution ID# rd06022011_406, it is perfectly legal on Cyclone IV to have a clock input with a different I/O voltage than the rest of the bank.

The problem is when I try to build a design with these clock pins defined, and declared as IO_STANDARD LVDS in the .qsf file, I get the following error (Quartus 11.1 SP2):

"Error (169298): I/O bank 8B contains input or bidirectional pins with I/O standards that make it impossible to choose a legal VCC_CLKIN value for the bank."

Is there a special IO_STANDARD or other special settings that I need to use to get Quartus to accept this supposedly legal combination of voltages?

1 Reply

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    13 years ago

    I think I may have found it...there is a second clock input in that bank which I had inadvertently defined as a 1.8V pin. So the conflict wasn't between the LVDS clock in 8B and the VCCIO in bank 8, but between two clock inputs in bank 8B with incompatible VCC_CLKIN requirements.