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Altera_Forum
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13 years ago

Cyclone IV: Error when mixing VCCIO, VCC_CLKIN in same bank

I am trying to compile a design for the Cyclone IV GX development board, which is based on an EP4CGX1150DF31C7. This board has bank 8 wired to a VCCIO of 1.8V. But within bank 8, there's the clocki...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
13 years ago

I think I may have found it...there is a second clock input in that bank which I had inadvertently defined as a 1.8V pin. So the conflict wasn't between the LVDS clock in 8B and the VCCIO in bank 8, but between two clock inputs in bank 8B with incompatible VCC_CLKIN requirements.