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Altera_Forum's avatar
Altera_Forum
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14 years ago

Cyclone IV DDR2 interface

Hello,

I'm trying to instantiate a DDR2 controller within a Qsys/NIOS II system. In Qsys, the generation of the system has no issues. When I try to compile the design, I get the error:

Error (15873): Output port DATAOUT of DDIO_OUT primitive "nios_core:cpu0|nios_core_ddr2:ddr2|nios_core_ddr2_controller_phy:nios_core_ddr2_controller_phy_inst|nios_core_ddr2_phy:nios_core_ddr2_phy_inst|nios_core_ddr2_phy_alt_mem_phy:nios_core_ddr2_phy_alt_mem_phy_inst|nios_core_ddr2_phy_alt_mem_phy_clk_reset:clk|altddio_bidir:DDR_CLK_OUT[0].ddr_clk_out_p|ddio_bidir_n5h:auto_generated|ddio_outa[0]" must drive input port I of an I/O OBUF primitive

I have made sure that every port that is an input is declared as an input, every inout declared as an inout, etc. Do you have any ideas on what else I need to check?

Thanks in advance.

9 Replies

  • Altera_Forum's avatar
    Altera_Forum
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    14 years ago

    Also note that I have followed the process that someone described in forum thread t=34105 (can't post links because my account is new).

    I can't get to the back-annotation step because the design won't compile.
  • Altera_Forum's avatar
    Altera_Forum
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    14 years ago

    http://alteraforum.com/forum/showthread.php?t=34105

    i don't know what i've missed in the referenced thread, but in my experience you have to run through Analysis and Synthesis to run pin_assignments.tcl for all of the assignments to take properly. overall i find those instructions confusing

    so, have you made it all the way through Analysis and Synthesis, then run the pin_assignments.tcl?
  • Altera_Forum's avatar
    Altera_Forum
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    14 years ago

    If I generate the DDR2 Controller with ALTMEMPHY in the Megawizard plug-in manager (outside of Qsys), and follow the instructions it gives me, I can get the project to compile. If I generate the DDR2 controller in a simple Qsys system (NIOS II processor, PLL, and DDR2 controller only), then I get the same error message. I have attached a .ZIP file with an example project that yields this error in Quartus 11.1 (I'm using it on Linux).

    Any ideas?

    BTW, the instructions that popped up after instantiating the controller from the Megawizard recommend that you run the pin_assignments.tcl file, assign the RAM pins to a desired bank, then run the quartus tools. I followed this process in both my Qsys and non-Qsys projects.
  • Altera_Forum's avatar
    Altera_Forum
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    14 years ago

    Hello there. I've come across the same problem.

    In a custom board with a DDR 2 the clock bidir pin was giving me the same errors during fitting.

    Looking at the .tcl in a reference design I found the following assigment and it resolved the problem.

    set_instance_assignment -name XSTL_INPUT_ALLOW_SE_BUFFER "ON" -to YOUR_DIFF_IO_CLK_P

    set_instance_assignment -name XSTL_INPUT_ALLOW_SE_BUFFER "ON" -to YOUR_DIFF_IO_CLK_N

    Use it on your diff clock bidir pins if will never be used this clock as input.

    Hope it helps.
  • Altera_Forum's avatar
    Altera_Forum
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    14 years ago

    Hi,

    I want to test one DDR2 memory using the example with ALTMEMPHY megafunction on cyclone IV, it compiles without errors or critical warnings, but when I use the ALTMEMPHY External Memory Interface Debug Toolkit it stops at the stage "Read resynchronisation phase calibration", anyone knows how to solve this?,

    Thank you.
  • Altera_Forum's avatar
    Altera_Forum
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    14 years ago

    Did you use all the scripts with locations and assignments from the ddr2 controller? The controller creates some .tcl files with dq group, output enable, etc assignments. You may have to add the .sdc files (also generated by the controller) and check timing.

    Is your cyclone on a custom board or on a development kit?