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Altera_Forum's avatar
Altera_Forum
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13 years ago

Cyclone IV DDR2 interface

Hello, I'm trying to instantiate a DDR2 controller within a Qsys/NIOS II system. In Qsys, the generation of the system has no issues. When I try to compile the design, I get the error: Erro...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
13 years ago

If I generate the DDR2 Controller with ALTMEMPHY in the Megawizard plug-in manager (outside of Qsys), and follow the instructions it gives me, I can get the project to compile. If I generate the DDR2 controller in a simple Qsys system (NIOS II processor, PLL, and DDR2 controller only), then I get the same error message. I have attached a .ZIP file with an example project that yields this error in Quartus 11.1 (I'm using it on Linux).

Any ideas?

BTW, the instructions that popped up after instantiating the controller from the Megawizard recommend that you run the pin_assignments.tcl file, assign the RAM pins to a desired bank, then run the quartus tools. I followed this process in both my Qsys and non-Qsys projects.