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Altera_Forum
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11 years ago

Cyclone III asynchronous input signal synchroinization problem.

Hello. I have a problem with the asynchronous input signal synchronization. I am trying to make the IIC_Slave based on Cyclone III FPGA Starter Kit. Altera Quartus II 13.1.0 x64 I saw 3 cases: ...
Altera_Forum's avatar
Altera_Forum
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11 years ago

I didn't analyze everything you posted, but I think you have the problem in case 2 because you are using different clocks with the two main blocks.

In particular, you are clocking BitCounter_Shifter with a signal generated by the synchronizer stage. This will lead to undefined timing relationships.

You must use the same 'true' clock (CClk) throughout the design, and you'd rather use it to synchronize the other signals.