Forum Discussion
Altera_Forum
Honored Contributor
14 years agoHi,
I think the problem is, that only output port C0 of the PLL can directly drive the dedicated external clock output. All other outputs must use a GCLK to drive the pin. Regards, HJSHi,
I think the problem is, that only output port C0 of the PLL can directly drive the dedicated external clock output. All other outputs must use a GCLK to drive the pin. Regards, HJS