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Altera_Forum
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15 years ago

Cyclone ALTPLL questions

Hello!

I have two simple questions regarding the use of PLL in a Cyclone I EP1C3 device.

1) I would like to have a 20 MHz input clock (inclk0) and two output clocks, one with the same frequency (c0) and one divided by four, 5 MHz (c1). The wizard would not create that division for some reason. Can anyone tell me why that is, and also how I may achieve my request?!

2) I have some considerations regarding pllena/areset/pfdena signals. They seem to be important to be implemented, although similar to each other. May I use all three of them, and furthermore, drive them with one single signal? (That would be the general active-low reset signal of the design, and I would pass it through a NOT gate before inputting to areset because of its active-high operation.)

I am in knowledge of the content of the related chapter in Altera Cyclone Handbook.

Thank you.

7 Replies

  • Altera_Forum's avatar
    Altera_Forum
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    15 years ago

    --- Quote Start ---

    I am in knowledge of the content of the related chapter in Altera Cyclone Handbook.

    --- Quote End ---

    Not actually, I fear. Please have a look at the clock multiplication & division point. The achievable out frequency is given by: 

    fC0 = fVCO/G0 = fIN × (M/(N × G0))

    With Cyclone I, all counters have a maximum count of 32, minimum VCO frequency is specified with 330 MHz. Output frequencies below about 12 MHz aren't feasible.

    Regarding control signals, you rarely need to utilize pllena or pfdena in standard designs. Areset may be helpful to force PLL resynchronization in cases, where the clock input isn't present continuously. The design parts depending on the PLL clock should be reset after PLL re-locking, with a synchronously released reset.
  • Altera_Forum's avatar
    Altera_Forum
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    15 years ago

    Ok as far as I understand my request is not achievable in this way. I will proceed using a self-created clock divider. I suppose that due to low frequencies that should not be a problem. Thank you very much!

  • Altera_Forum's avatar
    Altera_Forum
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    15 years ago

    FvM,

    do you think that a "ripple clock" would be that bad in the design, such as dividing 20 MHz to 5? It actually works in practice.

    I could also implement a 5 MHz oscillator in the circuit and multiply it to 20 MHz through the PLL.

    What do you think is best to do?

    Thanks.
  • Altera_Forum's avatar
    Altera_Forum
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    15 years ago

    ripple clocks can make timming closure harder, even for low frequencies.

    Take a look at http://www.alteraforum.com/forum/showthread.php?p=8501

    If possible, I'd rather use a the 20 MHz clock and a clock enable than a ripple clock.

    But using ripple clocks is far from a terribly bad idea.

    Using a 5 MHz clock and using a PLL to generate the 20 MHz clock is a better ideia, though.
  • Altera_Forum's avatar
    Altera_Forum
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    15 years ago

    Cyclone PLL won't accept 5 MHz input clock. If you use an external PLL, both clocks would be "unrelated" (have undefined phase relation) as well. A clock divider is definitely the way to go, if both clocks are intended to be used in the same design entity. If both clocks are driving completely separated entities, a ripple clock doesn't cáuse problems in timing closure.

  • Altera_Forum's avatar
    Altera_Forum
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    15 years ago

    Indeed, there is no way to use the internal PLL for my purposes.

    Anyway, ripple clock seems to work fine!

    Thank you!