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I am in knowledge of the content of the related chapter in Altera Cyclone Handbook.
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Not actually, I fear. Please have a look at the
clock multiplication & division point. The achievable out frequency is given by:
fC0 = fVCO/G0 = fIN × (M/(N × G0))
With Cyclone I, all counters have a maximum count of 32, minimum VCO frequency is specified with 330 MHz. Output frequencies below about 12 MHz aren't feasible.
Regarding control signals, you rarely need to utilize pllena or pfdena in standard designs. Areset may be helpful to force PLL resynchronization in cases, where the clock input isn't present continuously. The design parts depending on the PLL clock should be reset after PLL re-locking, with a synchronously released reset.
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