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Altera_Forum
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15 years ago

cyclone altpll max freq?

I am using cyclone ep1c20 grade 8, with an external clock 27M.

The altpll provides two clock outputs, 135M (c0) and 405M (c1 = 27x15). and 405M is to be used as a sampling clock for signal tap.

However, compilation fails at fitter, error message reads, "port clk1 output freq of 405M for PLL must be in range of 15.3-275MHz". Why it is so small? If that is the case, how to achieve a LVDS link with throughput > 275Mbps? manual says cyclone could achieve 640Mbps in LVDS.

Thanks.

5 Replies

  • Altera_Forum's avatar
    Altera_Forum
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    15 years ago

    the clock tree is only rated to 402MHz, not exactly sure where the 275MHz is coming from. from a quick check in the data sheet 275MHz is the fmax for the input clock of an emulated LVDS in x2-x10 modes.

  • Altera_Forum's avatar
    Altera_Forum
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    15 years ago

    The internal clock frequency for 640 MHz LVDS is 320 MHz, because LVDS always uses double data rate (DDIO) registers.

    The reported clock limitation is according to the grade -8 timing specifications in the Cyclone hardware handbook. The LVDS speed specification is summarized below:

    --- Quote Start ---

    Cyclone devices support different modes (× 1, × 2, × 4, × 7, × 8, and × 10) of operation with a maximum internal clock frequency of 405 MHz (-6 speed grade), 320 MHz (-7 speed grade), or 275 MHz (-8 speed grade), and a maximum data rate of 640 Mbps (-6 speed grade).

    --- Quote End ---

  • Altera_Forum's avatar
    Altera_Forum
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    15 years ago

    Thanks both.

    if the max. internal clock is 405 (-6 speed grade), how can 640Mbps being achieved? Must I use the altlvds? I have a parallel/serial module, driven by the fast clock = 275 (-8 speed grade), I think max. lvds speed is 275Mbps.

    Is there anything special in altlvds compared to usual p-s module?
  • Altera_Forum's avatar
    Altera_Forum
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    15 years ago

    As said above:

    --- Quote Start ---

    LVDS always uses double data rate (DDIO) registers

    --- Quote End ---