cyclone altpll max freq?

The internal clock frequency for 640 MHz LVDS is 320 MHz, because LVDS always uses double data rate (DDIO) registers.

The reported clock limitation is according to the grade -8 timing specifications in the Cyclone hardware handbook. The LVDS speed specification is summarized below:

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Cyclone devices support different modes (× 1, × 2, × 4, × 7, × 8, and × 10) of operation with a maximum internal clock frequency of 405 MHz (-6 speed grade), 320 MHz (-7 speed grade), or 275 MHz (-8 speed grade), and a maximum data rate of 640 Mbps (-6 speed grade).

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