Forum Discussion
Altera_Forum
Honored Contributor
8 years agoYes, I make changes to my source code (*.v), and start compilation. The source code was reverted back to prior state. I have to make the change again, then the changes stay. It doesn't matter if I run the component analysis or not, nor re-generate the HDL code in the QSYS helps. It's like deja vu all day. Don't know what is wrong with the Quartus.
I'm using Quartus Lite 16.1, working on DE1 evaluation board . I added a customized AVMM slave component in the GHRD.