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Altera_Forum
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12 years ago

Customize pattern generator created in Qsys

I did a design for Stratix V GX FPGA in order to transmit 3 independent channels. This design was created using qsys, also the pattern generator and the pattern_checker were created in qsys. Now I ne...
Altera_Forum's avatar
Altera_Forum
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12 years ago

Thank you Dave,

I have a question about the avalon_to_st_ram. In my case I want to initialize the RAM with a .mif file. In this case I think I don't need a FIFO, right? because I want to create a .mif fixed that it will be my pattern and I want that this .mif repeats every time. Or should my xcvr_low_latency_phy read from a fifo instead of the RAM directly? if I initialize my RAM, It is not necessary a dual-clock, isn't it?

I really appreciate your help.