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Altera_Forum
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12 years ago

Customize pattern generator created in Qsys

I did a design for Stratix V GX FPGA in order to transmit 3 independent channels. This design was created using qsys, also the pattern generator and the pattern_checker were created in qsys. Now I ne...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
12 years ago

Any help? Finally I have changed the design and I have created all the modules in megawizard connecting them to the master avalon bridge in qsys using an slave, furthermore I have created a PRBS where you can choose between PRBS 7, PRBS 15 or fix data, the problem is the width is only 40 bits. Actually I have a text file with 10^9 bits that I would like to introduce as my pattern. Is it possible with a dual-port ram introduce that number of bits? How would I be able to read the text file and introduce them as my input bitstream?

Thanks