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Altera_Forum
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12 years ago

Customize pattern generator created in Qsys

I did a design for Stratix V GX FPGA in order to transmit 3 independent channels. This design was created using qsys, also the pattern generator and the pattern_checker were created in qsys. Now I ne...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
12 years ago

In my current design, the pattern_out of the pattern generator is connected to a timing_adapter and the out of the timing adapter is connected tx_parallel_data of the low_latency protocol. This is a design for a "Transceiver Toolkit". But now I have replaced the pattern generator by an on-chip RAM but actually I don't know very well how I should to connect the RAM in this design. I attached my current qsys system in order to make more understandable.

Maybe should I change my design?

Thank you for your help.