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the problem is my pattern generator has an avalon streaming source connected to a timing adapter
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Why? A dual-port RAM can use two independent clocks, so your Avalon-ST source interface should not require a different clock than the sink, so you should not need a timing adapter.
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In my design I had a data_pattern_checker as well, Is it possible leave this interface in order to control the registers once I have replaced the data_pattern_generator by onchip_memory 2_0?
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Sure. Use SignalTap II to look at your pattern generator, or better yet, simulate the whole thing in Modelsim first.
Cheers,
Dave
Honored Contributor
