Honored Contributor
Honored ContributorI have tried to replace the pattern generator by a dual-port ram, then I have made the same connections in qsys as the pattern, the problem is my pattern generator has an avalon streaming source connected to a timing adapter, so I would need to connect the avalon memory mapped slave (S2) to the timing adapter like a source, but the design doesn´t let me the connection because it is a slave not a source. Moreover the clock1 has been connected to the general clock, clock2 has been connected to the protocol low_latency and s1 to the master. Is it that correct?
In my design I had a data_pattern_checker as well, Is it possible leave this interface in order to control the registers once I have replaced the data_pattern_generator by onchip_memory 2_0? Thank you.
