--- Quote Start ---
Is it possible introduce my own stream in a module created by qsys? Any idea? or should I need to create an external pattern generator programming it by verilog? Do you know if it would be possible load a file with my sequence of 1's and 0's from the PC to the FPGA?
--- Quote End ---
One option for a custom pattern generator is to use dual-port RAM. The pattern is then cyclic, with a maximum cycle length the size of the RAM (or smaller if you make it programmable). You can access one port of the RAM from Qsys, and the other from custom logic.
For the pattern generators I've written, I also have an Avalon-MM slave interface to control registers, so that I can enable and disable the pattern, and access bit-error-rate counters, etc.
Its easy to load the RAM from your PC if you use a JTAG-to-Avalon-MM bridge, eg., see this tutorial:
http://www.alterawiki.com/wiki/using_the_usb-blaster_as_an_sopc/qsys_avalon-mm_master_tutorial Cheers,
Dave
Honored Contributor
