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ThomasTessier's avatar
ThomasTessier
Icon for Occasional Contributor rankOccasional Contributor
2 years ago

Custom Built Avalon IP generating waitRequest but not being honored in the Interconnect.

I have a simple ArriaV based design using Quartus 21.1 that has a JTAG Master and BFM Master (for simulation). I am using a custom SPI module design that has a simple Avalon Slave interface. In my ...
ShengN_altera's avatar
ShengN_altera
Icon for Super Contributor rankSuper Contributor
2 years ago

Hi,

Check this Avalon® Verification IP Suite Design Example https://www.intel.com/content/www/us/en/support/programmable/support-resources/design-examples/horizontal/exm-avalon-verification-ip.html. Check design avlmm_1x1_verilog_test.

Below attached the design example avlm_avls_1x1_hw.tcl and simulation waveform. Make sure there's nothing missing or mismatch. In order to simulate with BFM Master, you may have to refer to Avalon-MM Slave BFM.

Thanks,

Best Regards,

Sheng

p/s: If any answer from the community or Intel Support are helpful, please feel free to give best answer.