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Altera_Forum
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13 years ago

Cryptic warning message when trying to constrain DDR input

I get the following warning from Quartus II 12.0sp1 when compiling a source synchronous DDR input interface to the FPGA: Warning (176441): The I/O pin adcIn[0] cannot meet the timing constraint...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
13 years ago

The internal delays were too high. Changing the design to use an extra clock phase allowed me to close timing.