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Altera_Forum
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13 years ago

Cryptic warning message when trying to constrain DDR input

I get the following warning from Quartus II 12.0sp1 when compiling a source synchronous DDR input interface to the FPGA: Warning (176441): The I/O pin adcIn[0] cannot meet the timing constraint...
Altera_Forum's avatar
Altera_Forum
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13 years ago

How could you not be meeting timing on the inputs with a -max and -min of 0? That basically says you have no external delays, so as long as you clock frequency is within spec, you should be meeting timing.