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Altera_Forum
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13 years ago

Cryptic warning message when trying to constrain DDR input

I get the following warning from Quartus II 12.0sp1 when compiling a source synchronous DDR input interface to the FPGA: Warning (176441): The I/O pin adcIn[0] cannot meet the timing constraint...
Altera_Forum's avatar
Altera_Forum
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13 years ago

Putting real numbers in for the input delay does not make this warning go away. The warning goes away only if the timing requirements are met. So, as far as I can tell, this warning is just telling me that the timing requirements were not achieved, which is kind of useless since the timing report already tells me that.