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Altera_Forum
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13 years ago

Cryptic warning message when trying to constrain DDR input

I get the following warning from Quartus II 12.0sp1 when compiling a source synchronous DDR input interface to the FPGA: Warning (176441): The I/O pin adcIn[0] cannot meet the timing constraint...
Altera_Forum's avatar
Altera_Forum
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13 years ago

Try putting some real values in for -max and -min. You've opened up the data valid window to its maximum, so the PLL may be having a hard time trying to figure out how to compensate for this. That's a guess as I've never seen this Warning before.