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You can't synchronously pass data between those clocks. A set_false_path would cut them. But you need to determine if that just makes the warning go away and there's still a problem, or if your design can handle an "unknown delay" on this path and work.
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27Mhz is the clock that samples signals asynchronously from cpu through an EMI interface.For some reasons,this clock is the main clock domain,and these parameters from CPU are sampled and stored here.while I need to sample some pulses that demand such a clock domain crossing work.
and I use two delay latches for sake of
metastablity.It seem that is doesn't work well.
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