Critical Warning: Timing requirements for slow timing model timing analysis were not

Have you added your sdc file to project to define timing constraints?

thanks for replying Kaz.

you need to add sdc file otherwise it defaults to some mystery violations... at least your clock frequency and io. look at examples of basic sdc in timequest resource centre altera website

we have added clock frequency by gng into edit settings and given value in individual clocks.. once we have done tht, we have got all these warnings..is it necessary to give the input delay for the design?

Are you using classic timing or timequest. Timequest needs sdc.

we are not using it Kaz.

For clock domain transfers (asynchronous signals) then you need synchronisers and set false path

actually our signals are synchronous.

If you switch to classic analyser then yes you can enter your clock(s) and tSU/tH/tCO and should be enough. You can also add cut paths, multicycle etc... through assignment editor per node.