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Altera_Forum
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14 years ago

Critical Warning: Timing requirements for slow timing model timing analysis were not

Hello, I'm trying out a Rs-232 Receiver and Transmitter code in Quartus || version 9.0 Build 235 06/17/2009 SJ full version, i ma getting a following critical warning during the compilation stage ...
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Altera_Forum
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14 years ago

thanks for replying Kaz.

we haven't included as sdc file as such.

We were just asked to write the code and try to implement on fpga.

they havent given any timing constraints except the operating clock frequency.