creating .pof file

The strange behavior is that it didn't work and then suddenly it started working.

gpio14 is coming from another FPGA with a very low frequency, there shouldn't be any timing issue since I don't use the clock for that process.

I ran it now for a few times and it works fine.

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The strange behavior is that it didn't work and then suddenly it started working.

gpio14 is coming from another FPGA with a very low frequency, there shouldn't be any timing issue since I don't use the clock for that process.

I ran it now for a few times and it works fine.

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Hi,

but you use the gpio14 as a clock ! (gpio14'event and gpio14 = '1'). If you use signals generated in this block in a block with a different clock

your design will not work stable. BTW did you connect yor reset signal ?

Kind regards

GPK

Hi,

I use the start_handshake_fsm signal only as a flag for another process. Though the other process uses another clock, it doesn't matter. As I said now its working.

I did connect the reset signal.

Might be that the FPGA was "stuck" and when I switched the power off for the night it fixed it?

--- Quote Start ---

Hi,

I use the start_handshake_fsm signal only as a flag for another process. Though the other process uses another clock, it doesn't matter. As I said now its working.

I did connect the reset signal.

Might be that the FPGA was "stuck" and when I switched the power off for the night it fixed it?

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Hi,

how did you synchronize your handshake signal in the other clock domain, in order to prevent metastability ? That could be the reason why your design is stuck .

Kind regards

GPK

Hi,

I put an if condition on the other process:

if (rising_edge(clk) and start_handshake_fsm = '1') then....

is that a problem?

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Hi,

I put an if condition on the other process:

if (rising_edge(clk) and start_handshake_fsm = '1') then....

is that a problem?

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Hi,

this could be a problem. I assume that "clk" is much faster then the gpio signal.

In this case you should latch the handshake signal with two registers in a row clocked by "clk". For more info's look:

http://www.fpga4fun.com/crossclockdomain1.html

Kind regards

GPK