Creating a VWF file

you will need to use Quartus II 9.1sp2 or earlier for the VWF editor and/or Quartus II Simulator

Thank you very much for the answer. I'm surprised that I wasn't able to find this information out anywhere else, but I appreciate the help.

for existing users they have warned for a couple versions that the Simulator would be going away. it might say in the release notes that it was removed, but it might not explicitly mention the .vwf editor

Haha yeah I literally just found the Release Notes for the new 10.0 version, and they say that the wave file simulation has been completely removed. So I guess I will have to figure out this ModelSim thing. Oh well... so much for buying a $130 text book that uses a different version of quartus...

If you prefer to follow the tutorial, you may want to install Quartus V9.1 in addition. It's still available in the software archives.

i agree, you might still use 9.1sp2 for learning and take on ModelSim as you become more familiar with the fundamentals

YES! This is exactly what I was looking for. Thanks to both of you for the help!

I have been following this thread with interest. I am writing the new edition of my Prentice-Hall Digital Electronics textbook which is geared toward the freshman-level ET or EE. Covering testbenches to import into ModelSIM at this level is way over their head yet producing simulations is SUCH a great learning tool.

The only reason I'm going with 9.1 is because the text book I'm using (Fundamentals of Digital Logic with VHDL Design 3rd Ed., Stephen Brown) uses vector waveform files to simulate digital circuits, so that is what we are using in class. I think it might be a good idea to teach ModelSIM and testbenches since Altera is only offering these tools. But on the other hand, it was really easy to learn the simulation in the 9.1 version. So it could be better for beginners.

Bill, yes it seems like that is the best option. you could provide a test bench cookbook if you wanted to concentrate on synthesize HDL. this way students could paste in a clock generating process, reset generating process, data input generating process. then they would just have to do some basic port mapping to the DUT instance. copy+pasting a basic data_input <= "00"; wait for 10 ns; sequence seems reasonable and intuitive to me. then again i found creating test bench waveforms somewhat tedious even as a beginner :)