creating a vhdl package in quatus II 6.1 web ed.

hi,

im a newbie by using quartus II and also vhdl code,

im reading a book is CIRCUIT DESIGN IN VHDL to learn :)

i need to implement the vhdl code in quartus II, im confused by compiling the vhdl package

am i create a library in C:\altera\61\quartus\libraries ? or just add the package in Project>Add/Remove Files in Project.

could you help me?:confused:

and if there is a tutorial that is using vhdl with vhdl package in quartus II,it will be helpful for me.

this is the package(mult_package.vhd)

LIBRARY ieee;

USE ieee.std_logic_1164.all;

USE ieee.std_logic_arith.all;

PACKAGE pack IS

FUNCTION mult(a,b:UNSIGNED) RETURN UNSIGNED;

END pack

PACKAGE BODY pack IS

FUNCTION mult(a,b:UNSIGNED) RETURN UNSIGNED IS

CONSTANT max: INTEGER :=a'LENGTH + b'LENGTH - 1;

VARIABLE aa: UNSIGNED (max DOWNTO 0):=

(max DOWNTO a'LENGTH =>'0')

& a(a'LENGTH-1 DOWNTO 0);

VARIABLE prod: UNSIGNED(max DOWNTO 0):=(OTHERS => '0');

BEGIN

FOR: IN 0 TO a'LENGTH-1 LOOP

IF (b(i)='1') THEN prod:=prod+aa;

END IF;

aa:= aa(max-1 DOWNTO 0) & '0';

END LOOP;

RETURN prod;

END mult;

END pack;

and the main code (multiplier.vhd)

LIBRARY ieee;

USE ieee.std_logic_1164.all;

USE ieee.std_logic_arith.all;

USE work.mult_package.all;

ENTITY multiplier IS

GENERIC (size: INTEGER := 4);

PORT (a,b:IN UNSIGNED(size-1 DOWNTO 0);

y:OUT UNSIGNED(2*size-1 DOWNTO 0));

END multiplier;

ARCHITECTURE behaviour OF multiplier IS

BEGIN

y<= mult(a,b);

END behaviour;

im confused about using the libraries were created

there are the steps that i did.

created a project named multiplier then

write these two in text editor

then i add these in project>add/remove files in project

then start compilation

these errors belongs to mult_package.vhd file

Error (10500): VHDL syntax error at mult_package.vhd(7) near text "PACKAGE"; expecting ";"

Error (10500): VHDL syntax error at mult_package.vhd(8) near text "IS"; expecting ";"

Error (10500): VHDL syntax error at mult_package.vhd(14) near text "BEGIN"; expecting "end", or a declaration statement

Error (10396): VHDL syntax error at mult_package.vhd(21): name used in construct must match previously specified name "pack"

Error (10523): Ignored construct pack at mult_package.vhd(4) due to previous errors

Error (10500): VHDL syntax error at mult_package.vhd(22) near text "END"; expecting "entity", or "architecture", or "use", or "library", or "package", or "configuration"

thank you.