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Altera_Forum's avatar
Altera_Forum
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15 years ago

created a proj in quartus 6.0 upgrding to 9.0 compile problem

HI,

we have done a project in quartus 6.0 and finished also.

now our client asking for rs-decoding feature, and they only providing IPCORE. but they are giving only quartus 9.0 IPCORE.

now i compiled my project(with out any changes) in quarus9.0 but i am not able to reach the required(what i achieved in 6.0) Fmax.

project done using ep2s130f and consumes 40% of resources, required Fmax=250Mhz

give some suggestions/ideas to make it easier.

Thanks

2 Replies

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    15 years ago

    Make sure you are using the Timequest analyser instead of the classic timing analyser in your project, it will probably be more efficient.

    In the Tolls menu you have an 'Advisors' submenu. Into in, run the Timing Optimization advisor. It will have a look at your project and can suggest a few things to increase your fmax.
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    15 years ago

    thanks for reply,

    i have selected timequest and generated <>.sdc file from sdc gui with older settings. but i cont found critical path report,it showing only setup,hold slack timings.

    guide me to find critical path.

    ============================

    ihave a doubt that timing analyzers are only for showing reports or for auto optimization of code also?

    it is running after assembler, so where is the point of timing optimization of the code? or fitter only itself optimizes?

    ==========================

    thanks in advance